Architecture >> Pgp2bAxiWrapper::rtl

Signals
axilClk	sl
axilRst	sl
axilReadMaster	AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
axilReadSlave	AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_INIT_C
axilWriteMaster	AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
axilWriteSlave	AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_INIT_C
pgpTxIn	Pgp2bTxInType := PGP2B_TX_IN_INIT_C
pgpRxIn	Pgp2bRxInType := PGP2B_RX_IN_INIT_C
locTxIn	Pgp2bTxInType := ( flush = > ' 0 ' , opCodeEn = > ' 0 ' , opCode = > ( others = > ' 0 ' ) , locData = > x " C3 " , flowCntlDis = > ' 0 ' , resetTx = > ' 0 ' , resetGt = > ' 0 ' )
pgpTxOut	Pgp2bTxOutType := ( locOverflow = > " 0101 " , locPause = > " 0011 " , phyTxReady = > ' 1 ' , linkReady = > ' 1 ' , frameTx = > ' 0 ' , frameTxErr = > ' 0 ' )
pgpRxOut	Pgp2bRxOutType := ( phyRxReady = > ' 1 ' , linkReady = > ' 1 ' , linkPolarity = > " 10 " , frameRx = > ' 0 ' , frameRxErr = > ' 0 ' , cellError = > ' 0 ' , linkDown = > ' 0 ' , linkError = > ' 0 ' , opCodeEn = > ' 0 ' , opCode = > ( others = > ' 0 ' ) , remLinkReady = > ' 1 ' , remLinkData = > x " A5 " , remOverflow = > " 0011 " , remPause = > " 0101 " )
statusWord	slv ( 63 downto 0 )
statusSend	sl
txDiffCtrl	slv ( 4 downto 0 )
txPreCursor	slv ( 4 downto 0 )
txPostCursor	slv ( 4 downto 0 )

Instantiations
u_sh	SlaveAxiLiteIpIntegrator <Entity SlaveAxiLiteIpIntegrator>
u_dut	Pgp2bAxi <Entity Pgp2bAxi>

The documentation for this design unit was generated from the following file:

Signals

Instantiations