MicroblazeBasicCoreWrapper Entity Reference

Inheritance diagram for MicroblazeBasicCoreWrapper:

Collaboration diagram for MicroblazeBasicCoreWrapper:

Entities
MicroblazeBasicCoreWrapper.mapping	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
StdRtlPkg	Package <StdRtlPkg>
AxiStreamPkg	Package <AxiStreamPkg>
AxiLitePkg	Package <AxiLitePkg>
SsiPkg	Package <SsiPkg>

Generics
TPD_G	time := 1 ns
AXIL_RESP_G	boolean := false
AXIL_ADDR_MSB_G	boolean := false
AXIL_ADDR_SEL_G	boolean := false

Ports
mAxilWriteMaster	out	AxiLiteWriteMasterType
mAxilWriteSlave	in	AxiLiteWriteSlaveType
mAxilReadMaster	out	AxiLiteReadMasterType
mAxilReadSlave	in	AxiLiteReadSlaveType
sAxisMaster	in	AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C
sAxisSlave	out	AxiStreamSlaveType
mAxisMaster	out	AxiStreamMasterType
mAxisSlave	in	AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C
interrupt	in	slv ( 7 downto 0 ) := ( others = > ' 0 ' )
clk	in	sl
pllLock	in	sl := ' 1 '
rst	in	sl

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The documentation for this design unit was generated from the following files:

• xilinx/general/microblaze/bypass/MicroblazeBasicCoreWrapper.vhd
• xilinx/general/microblaze/generate/MicroblazeBasicCoreWrapper.vhd