MicroblazeBasicCoreWrapper.mapping Architecture Reference

Architecture >> MicroblazeBasicCoreWrapper::mapping

Components
MicroblazeBasicCore

Signals
awaddr	slv ( 31 downto 0 )
araddr	slv ( 31 downto 0 )
bresp	slv ( 1 downto 0 )
rresp	slv ( 1 downto 0 )
addr_sel	sl
txMaster	AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C
txSlave	AxiStreamSlaveType

Instantiations
u_microblaze	microblazebasiccore
u_insertsof	SsiInsertSof <Entity SsiInsertSof>

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The documentation for this design unit was generated from the following files:

• xilinx/general/microblaze/bypass/MicroblazeBasicCoreWrapper.vhd
• xilinx/general/microblaze/generate/MicroblazeBasicCoreWrapper.vhd