Max5443.rtl Architecture Reference

Architecture >> Max5443::rtl

Processes
comb	( axilReadMaster , axilRst , axilWriteMaster , r )
seq	( axilClk )

Constants
REG_INIT_C	RegType := ( vDacSetting = > ( others = > ( others = > ' 0 ' ) ) , axilReadSlave = > AXI_LITE_READ_SLAVE_INIT_C , axilWriteSlave = > AXI_LITE_WRITE_SLAVE_INIT_C )

Signals
r	RegType := REG_INIT_C
rin	RegType
dacDinSig	slv ( NUM_CHIPS_G- 1 downto 0 )
dacSclkSig	slv ( NUM_CHIPS_G- 1 downto 0 )
dacClrbSig	slv ( NUM_CHIPS_G- 1 downto 0 )

Records
RegType

Instantiations
u_daccntrl	Max5443DacCntrl <Entity Max5443DacCntrl>

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The documentation for this design unit was generated from the following file:

• devices/Maxim/rtl/Max5443.vhd