Max5443 Entity Reference

Inheritance diagram for Max5443:

Collaboration diagram for Max5443:

Entities
Max5443.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_unsigned
std_logic_arith
StdRtlPkg	Package <StdRtlPkg>
AxiLitePkg	Package <AxiLitePkg>

Generics
TPD_G	time := 1 ns
CLK_PERIOD_G	real := 10 . 0E - 9
NUM_CHIPS_G	positive := 1

Ports
axilClk	in	sl
axilRst	in	sl
axilReadMaster	in	AxiLiteReadMasterType
axilReadSlave	out	AxiLiteReadSlaveType
axilWriteMaster	in	AxiLiteWriteMasterType
axilWriteSlave	out	AxiLiteWriteSlaveType
dacSclk	out	sl
dacDin	out	sl
dacCsb	out	slv ( NUM_CHIPS_G- 1 downto 0 )
dacClrb	out	sl

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The documentation for this design unit was generated from the following file:

• devices/Maxim/rtl/Max5443.vhd