Max5443DacCntrl Entity Reference

Inheritance diagram for Max5443DacCntrl:

Entities
Max5443DacCntrl.rtl	architecture

Libraries
ieee

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned

Generics
TPD_G	time := 1 ns

Ports
sysClk	in	std_logic
sysClkRst	in	std_logic
dacData	in	std_logic_vector ( 15 downto 0 )
dacDin	out	std_logic
dacSclk	out	std_logic
dacCsL	out	std_logic
dacClrL	out	std_logic

---

The documentation for this design unit was generated from the following file:

• devices/Maxim/rtl/Max5443DacCntrl.vhd