Max5443DacCntrl.rtl Architecture Reference

Architecture >> Max5443DacCntrl::rtl

Processes
PROCESS_195	( sysClk )
PROCESS_196	( sysClk , sysClkRst )
PROCESS_197	( sysClk , sysClkRst )
PROCESS_198	( curState , dacStrobe , intBit , intClkEn , intData )

Constants
ST_IDLE	std_logic_vector ( 1 downto 0 ) := " 01 "
ST_WAIT	std_logic_vector ( 1 downto 0 ) := " 10 "
ST_SHIFT	std_logic_vector ( 1 downto 0 ) := " 11 "

Signals
intData	std_logic_vector ( 15 downto 0 )
intCnt	std_logic_vector ( 2 downto 0 )
intClk	std_logic
intClkEn	std_logic
intBitRst	std_logic
intBitEn	std_logic
intBit	std_logic_vector ( 3 downto 0 )
nxtDin	std_logic
nxtCsL	std_logic
dacStrobe	std_logic
curState	std_logic_vector ( 1 downto 0 )
nxtState	std_logic_vector ( 1 downto 0 )

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The documentation for this design unit was generated from the following file:

• devices/Maxim/rtl/Max5443DacCntrl.vhd