JesdTxLane.rtl Architecture Reference

Architecture >> JesdTxLane::rtl

Signals
s_dataValid	sl
s_ila	sl
s_refDetected	sl
s_sampleDataMux	slv ( r_jesdGtTx.data ' range )
s_sampleKMux	slv ( r_jesdGtTx.dataK ' range )
s_ilaDataMux	slv ( r_jesdGtTx.data ' range )
s_ilaKMux	slv ( r_jesdGtTx.dataK ' range )
s_commaDataMux	slv ( r_jesdGtTx.data ' range )
s_commaKMux	slv ( r_jesdGtTx.dataK ' range )
s_data_sel	slv ( 1 downto 0 )

Instantiations
syncfsm_inst	JesdSyncFsmTx <Entity JesdSyncFsmTx>
ilasgen_inst	JesdIlasGen <Entity JesdIlasGen>
alignchgen_inst	JesdAlignChGen <Entity JesdAlignChGen>
syncfsm_inst	JesdSyncFsmTx <Entity JesdSyncFsmTx>
ilasgen_inst	JesdIlasGen <Entity JesdIlasGen>
alignchgen_inst	JesdAlignChGen <Entity JesdAlignChGen>

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/JesdTxLane.vhd
• protocols/jesd204b/rtl/JesdTxLane.vhd