JesdAlignChGen Entity Reference

Inheritance diagram for JesdAlignChGen:

Entities
JesdAlignChGen.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_unsigned
std_logic_arith
StdRtlPkg	Package <StdRtlPkg>
Jesd204bpkg

Generics
TPD_G	time := 1 ns
F_G	positive := 2

Ports
clk	in	sl
rst	in	sl
enable_i	in	sl
scrEnable_i	in	sl
lmfc_i	in	sl
dataValid_i	in	sl
inv_i	in	sl := ' 0 '
sampleData_i	in	slv ( GT_WORD_SIZE_C* 8 - 1 downto 0 )
sampleData_o	out	slv ( GT_WORD_SIZE_C* 8 - 1 downto 0 )
sampleK_o	out	slv ( GT_WORD_SIZE_C- 1 downto 0 )

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/JesdAlignChGen.vhd
• protocols/jesd204b/rtl/JesdAlignChGen.vhd