JesdAlignChGen.rtl Architecture Reference

Architecture >> JesdAlignChGen::rtl

Processes
comb	( dataValid_i , enable_i , inv_i , lmfc_i , r , rst , sampleData_i , scrEnable_i )
seq	( clk )
comb	( dataValid_i , enable_i , inv_i , lmfc_i , r , rst , sampleData_i , scrEnable_i )
seq	( clk )

Constants
SAMPLES_IN_WORD_C	positive := ( GT_WORD_SIZE_C/ F_G )
REG_INIT_C	RegType := ( sampleDataReg = > ( others = > ' 0 ' ) , sampleDataInv = > ( others = > ' 0 ' ) , sampleDataD1 = > ( others = > ' 0 ' ) , sampleDataD2 = > ( others = > ' 0 ' ) , sampleKD1 = > ( others = > ' 0 ' ) , lfsr = > ( others = > ' 0 ' ) , lmfcD1 = > ' 0 ' )

Signals
r	RegType := REG_INIT_C
rin	RegType

Records
RegType

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/JesdAlignChGen.vhd
• protocols/jesd204b/rtl/JesdAlignChGen.vhd