Jesd204bLoopbackWrapper Entity Reference

Inheritance diagram for Jesd204bLoopbackWrapper:

Collaboration diagram for Jesd204bLoopbackWrapper:

Entities
Jesd204bLoopbackWrapper.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
numeric_std
StdRtlPkg	Package <StdRtlPkg>
AxiLitePkg	Package <AxiLitePkg>
Jesd204bPkg	Package <Jesd204bPkg>

Generics
TPD_G	time := 1 ns
F_G	positive := 2
K_G	positive := 32
L_G	positive range 1 to 16 := 2
DID_G	slv ( 7 downto 0 ) := ( others = > ' 0 ' )
BID_G	slv ( 3 downto 0 ) := ( others = > ' 0 ' )
M_G	slv ( 7 downto 0 ) := ( others = > ' 0 ' )
N_G	slv ( 4 downto 0 ) := ( others = > ' 0 ' )
NPRIME_G	slv ( 4 downto 0 ) := ( others = > ' 0 ' )
CS_G	slv ( 1 downto 0 ) := ( others = > ' 0 ' )
S_G	slv ( 4 downto 0 ) := ( others = > ' 0 ' )
HD_G	sl := ' 0 '
CF_G	slv ( 4 downto 0 ) := ( others = > ' 0 ' )
ADDR_WIDTH	positive := 12

Ports
devClk_i	in	sl
devRst_i	in	sl
sysRef_i	in	sl
S_AXI_TX_ACLK	in	std_logic
S_AXI_TX_ARESETN	in	std_logic
S_AXI_TX_AWADDR	in	std_logic_vector ( ADDR_WIDTH- 1 downto 0 )
S_AXI_TX_AWPROT	in	std_logic_vector ( 2 downto 0 )
S_AXI_TX_AWVALID	in	std_logic
S_AXI_TX_AWREADY	out	std_logic
S_AXI_TX_WDATA	in	std_logic_vector ( 31 downto 0 )
S_AXI_TX_WSTRB	in	std_logic_vector ( 3 downto 0 )
S_AXI_TX_WVALID	in	std_logic
S_AXI_TX_WREADY	out	std_logic
S_AXI_TX_BRESP	out	std_logic_vector ( 1 downto 0 )
S_AXI_TX_BVALID	out	std_logic
S_AXI_TX_BREADY	in	std_logic
S_AXI_TX_ARADDR	in	std_logic_vector ( ADDR_WIDTH- 1 downto 0 )
S_AXI_TX_ARPROT	in	std_logic_vector ( 2 downto 0 )
S_AXI_TX_ARVALID	in	std_logic
S_AXI_TX_ARREADY	out	std_logic
S_AXI_TX_RDATA	out	std_logic_vector ( 31 downto 0 )
S_AXI_TX_RRESP	out	std_logic_vector ( 1 downto 0 )
S_AXI_TX_RVALID	out	std_logic
S_AXI_TX_RREADY	in	std_logic
S_AXI_RX_ACLK	in	std_logic
S_AXI_RX_ARESETN	in	std_logic
S_AXI_RX_AWADDR	in	std_logic_vector ( ADDR_WIDTH- 1 downto 0 )
S_AXI_RX_AWPROT	in	std_logic_vector ( 2 downto 0 )
S_AXI_RX_AWVALID	in	std_logic
S_AXI_RX_AWREADY	out	std_logic
S_AXI_RX_WDATA	in	std_logic_vector ( 31 downto 0 )
S_AXI_RX_WSTRB	in	std_logic_vector ( 3 downto 0 )
S_AXI_RX_WVALID	in	std_logic
S_AXI_RX_WREADY	out	std_logic
S_AXI_RX_BRESP	out	std_logic_vector ( 1 downto 0 )
S_AXI_RX_BVALID	out	std_logic
S_AXI_RX_BREADY	in	std_logic
S_AXI_RX_ARADDR	in	std_logic_vector ( ADDR_WIDTH- 1 downto 0 )
S_AXI_RX_ARPROT	in	std_logic_vector ( 2 downto 0 )
S_AXI_RX_ARVALID	in	std_logic
S_AXI_RX_ARREADY	out	std_logic
S_AXI_RX_RDATA	out	std_logic_vector ( 31 downto 0 )
S_AXI_RX_RRESP	out	std_logic_vector ( 1 downto 0 )
S_AXI_RX_RVALID	out	std_logic
S_AXI_RX_RREADY	in	std_logic
extData_0_i	in	slv ( GT_WORD_SIZE_C* 8 - 1 downto 0 )
extData_1_i	in	slv ( GT_WORD_SIZE_C* 8 - 1 downto 0 )
nSync_TX_i	in	slv ( L_G- 1 downto 0 )
nSync_RX_o	out	sl
gtTxData_0_o	out	slv ( GT_WORD_SIZE_C* 8 - 1 downto 0 )
gtTxDataK_0_o	out	slv ( GT_WORD_SIZE_C- 1 downto 0 )
gtTxData_1_o	out	slv ( GT_WORD_SIZE_C* 8 - 1 downto 0 )
gtTxDataK_1_o	out	slv ( GT_WORD_SIZE_C- 1 downto 0 )
gtRxData_0_i	in	slv ( GT_WORD_SIZE_C* 8 - 1 downto 0 )
gtRxDataK_0_i	in	slv ( GT_WORD_SIZE_C- 1 downto 0 )
gtRxDispErr_0_i	in	slv ( GT_WORD_SIZE_C- 1 downto 0 )
gtRxDecErr_0_i	in	slv ( GT_WORD_SIZE_C- 1 downto 0 )
gtRxRstDone_0_i	in	sl
gtRxCdrStable_0_i	in	sl
gtRxData_1_i	in	slv ( GT_WORD_SIZE_C* 8 - 1 downto 0 )
gtRxDataK_1_i	in	slv ( GT_WORD_SIZE_C- 1 downto 0 )
gtRxDispErr_1_i	in	slv ( GT_WORD_SIZE_C- 1 downto 0 )
gtRxDecErr_1_i	in	slv ( GT_WORD_SIZE_C- 1 downto 0 )
gtRxRstDone_1_i	in	sl
gtRxCdrStable_1_i	in	sl
sampleData_0_o	out	slv ( GT_WORD_SIZE_C* 8 - 1 downto 0 )
sampleData_1_o	out	slv ( GT_WORD_SIZE_C* 8 - 1 downto 0 )
dataValid_0_o	out	sl
dataValid_1_o	out	sl
sysRefDbg_o	out	sl

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The documentation for this design unit was generated from the following file:

• protocols/jesd204b/wrappers/Jesd204bLoopbackWrapper.vhd