IprogUltraScale.rtl Architecture Reference

Architecture >> IprogUltraScale::rtl

Functions
slv	selectMapBitSwapping ( input: in slv )

Processes
comb	( bootAddressSync , icape2Rst , r , rdy , startEdge )
seq	( icape2Clk )

Constants
REG_INIT_C	RegType := ( state = > IDLE_S , csl = > ' 1 ' , rdy = > ' 1 ' , rnw = > ' 1 ' , cnt = > ( others = > ' 0 ' ) , configData = > ( others = > ' 0 ' ) , bootAddress = > ( others = > ' 0 ' ) )

Types
StateType	( IDLE_S , PROG_S )

Signals
r	RegType := REG_INIT_C
rin	RegType
divClk	sl
icape2Clk	sl
icape2Rst	sl
startEdge	sl
rdy	sl
bootAddressSync	slv ( 31 downto 0 )

Records
RegType

Instantiations
bufgce_div_inst	bufgce_div
rstsync_inst	RstSync <Entity RstSync>
synchronizeroneshot_1	SynchronizerOneShot <Entity SynchronizerOneShot>
synchronizervector_1	SynchronizerVector <Entity SynchronizerVector>
icape3_inst	icape3

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The documentation for this design unit was generated from the following file:

• xilinx/UltraScale/general/rtl/IprogUltraScale.vhd