HtspTxFifo.mapping Architecture Reference

Architecture >> HtspTxFifo::mapping

Signals
flushedTxMasters	AxiStreamMasterArray ( NUM_VC_G- 1 downto 0 )
flushedTxCtrl	AxiStreamCtrlArray ( NUM_VC_G- 1 downto 0 )
fifoTxMasters	AxiStreamMasterArray ( NUM_VC_G- 1 downto 0 )
fifoTxSlaves	AxiStreamSlaveArray ( NUM_VC_G- 1 downto 0 )
linkReady	sl
flushEn	slv ( NUM_VC_G- 1 downto 0 )
htspReset	sl
appResets	slv ( NUM_VC_G- 1 downto 0 )

Instantiations
u_htsprst	RstPipeline <Entity RstPipeline>
u_apprst	RstPipeline <Entity RstPipeline>
u_flushsync	Synchronizer <Entity Synchronizer>
u_flush	AxiStreamFlush <Entity AxiStreamFlush>
u_resize	AxiStreamFifoV2 <Entity AxiStreamFifoV2>
u_sof	SsiInsertSof <Entity SsiInsertSof>
u_htsprst	RstPipeline <Entity RstPipeline>
u_apprst	RstPipeline <Entity RstPipeline>
u_flushsync	Synchronizer <Entity Synchronizer>
u_flush	AxiStreamFlush <Entity AxiStreamFlush>
u_resize	AxiStreamFifoV2 <Entity AxiStreamFifoV2>
u_sof	SsiInsertSof <Entity SsiInsertSof>

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/HtspTxFifo.vhd
• protocols/htsp/core/rtl/HtspTxFifo.vhd