GtyUltraScaleQuadPll Entity Reference

Inheritance diagram for GtyUltraScaleQuadPll:

Collaboration diagram for GtyUltraScaleQuadPll:

Entities
GtyUltraScaleQuadPll.mapping	architecture

Libraries
ieee
surf
unisim

Use Clauses
std_logic_1164
StdRtlPkg	Package <StdRtlPkg>
AxiLitePkg	Package <AxiLitePkg>
vcomponents

Generics
TPD_G	time := 1 ns
SIM_DEVICE	string := " ULTRASCALE_PLUS "
SIM_MODE	string := " FAST "
SIM_RESET_SPEEDUP	string := " TRUE "
BIAS_CFG0_G	slv ( 15 downto 0 ) := x " 0000 "
BIAS_CFG1_G	slv ( 15 downto 0 ) := x " 0000 "
BIAS_CFG2_G	slv ( 15 downto 0 ) := x " 0524 "
BIAS_CFG3_G	slv ( 15 downto 0 ) := x " 0041 "
BIAS_CFG4_G	slv ( 15 downto 0 ) := x " 0010 "
BIAS_CFG_RSVD_G	slv ( 15 downto 0 ) := X " 0000 "
COMMON_CFG0_G	slv ( 15 downto 0 ) := x " 0000 "
COMMON_CFG1_G	slv ( 15 downto 0 ) := x " 0000 "
POR_CFG_G	slv ( 15 downto 0 ) := x " 0000 "
PPF_CFG_G	Slv16Array ( 1 downto 0 ) := ( others = > x " 0600 " )
QPLL0CLKOUT_RATE_G	string := " HALF "
QPLL1CLKOUT_RATE_G	string := " HALF "
QPLL_CFG0_G	Slv16Array ( 1 downto 0 ) := ( others = > x " 331C " )
QPLL_CFG1_G	Slv16Array ( 1 downto 0 ) := ( others = > x " D038 " )
QPLL_CFG1_G3_G	Slv16Array ( 1 downto 0 ) := ( others = > x " D038 " )
QPLL_CFG2_G	Slv16Array ( 1 downto 0 ) := ( others = > x " 0FC0 " )
QPLL_CFG2_G3_G	Slv16Array ( 1 downto 0 ) := ( others = > x " 0FC0 " )
QPLL_CFG3_G	Slv16Array ( 1 downto 0 ) := ( others = > x " 0120 " )
QPLL_CFG4_G	Slv16Array ( 1 downto 0 ) := ( others = > x " 0002 " )
QPLL_CP_G	Slv10Array ( 1 downto 0 ) := ( others = > " 0011111111 " )
QPLL_CP_G3_G	Slv10Array ( 1 downto 0 ) := ( others = > " 0000001111 " )
QPLL_FBDIV_G	NaturalArray ( 1 downto 0 ) := ( others = > 66 )
QPLL_FBDIV_G3_G	NaturalArray ( 1 downto 0 ) := ( others = > 160 )
QPLL_INIT_CFG0_G	Slv16Array ( 1 downto 0 ) := ( others = > x " 02B2 " )
QPLL_INIT_CFG1_G	Slv8Array ( 1 downto 0 ) := ( others = > x " 00 " )
QPLL_LOCK_CFG_G	Slv16Array ( 1 downto 0 ) := ( others = > x " 25E8 " )
QPLL_LOCK_CFG_G3_G	Slv16Array ( 1 downto 0 ) := ( others = > x " 25E8 " )
QPLL_LPF_G	Slv10Array ( 1 downto 0 ) := ( others = > " 1000111111 " )
QPLL_LPF_G3_G	Slv10Array ( 1 downto 0 ) := ( others = > " 0111010101 " )
QPLL_REFCLK_DIV_G	NaturalArray ( 1 downto 0 ) := ( others = > 1 )
QPLL_SDM_CFG0_G	Slv16Array ( 1 downto 0 ) := ( others = > x " 0080 " )
QPLL_SDM_CFG1_G	Slv16Array ( 1 downto 0 ) := ( others = > x " 0000 " )
QPLL_SDM_CFG2_G	Slv16Array ( 1 downto 0 ) := ( others = > x " 0000 " )
QPLL_REFCLK_SEL_G	Slv3Array ( 1 downto 0 ) := ( others = > " 001 " )
EN_DRP_G	boolean := true

Ports
qPllRefClk	in	slv ( 1 downto 0 )
qPllOutClk	out	slv ( 1 downto 0 )
qPllOutRefClk	out	slv ( 1 downto 0 )
qPllFbClkLost	out	slv ( 1 downto 0 )
qPllLock	out	slv ( 1 downto 0 )
qPllLockDetClk	in	slv ( 1 downto 0 )
qPllRefClkLost	out	slv ( 1 downto 0 )
qPllPowerDown	in	slv ( 1 downto 0 ) := " 00 "
qPllReset	in	slv ( 1 downto 0 )
axilClk	in	sl := ' 0 '
axilRst	in	sl := ' 0 '
axilReadMaster	in	AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
axilReadSlave	out	AxiLiteReadSlaveType
axilWriteMaster	in	AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
axilWriteSlave	out	AxiLiteWriteSlaveType

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The documentation for this design unit was generated from the following file:

• xilinx/UltraScale+/gtyUs+/rtl/GtyUltraScaleQuadPll.vhd