Gtp7TxRst.RTL Architecture Reference

Architecture >> Gtp7TxRst::RTL

Processes
PROCESS_436	( STABLE_CLOCK )
timeouts	( STABLE_CLOCK )
mmcm_lock_wait	( STABLE_CLOCK )
PROCESS_437	( TXUSERCLK )
PROCESS_438	( STABLE_CLOCK )
PROCESS_439	( STABLE_CLOCK )
PROCESS_440	( STABLE_CLOCK )
timeout_buffer_bypass	( TXUSERCLK )
PROCESS_441	( PLL0REFCLKLOST , PLL1REFCLKLOST , qPllTxSelect )
reset_fsm	( STABLE_CLOCK )

Libraries
surf

Constants
MMCM_LOCK_CNT_MAX	integer := 1024
STARTUP_DELAY	integer := 500
WAIT_CYCLES	integer := STARTUP_DELAY/ STABLE_CLOCK_PERIOD
WAIT_MAX	integer := WAIT_CYCLES+ 10
WAIT_TIMEOUT_2ms	integer := 2000000 / STABLE_CLOCK_PERIOD
WAIT_TLOCK_MAX	integer := 100000 / STABLE_CLOCK_PERIOD
WAIT_TIMEOUT_500us	integer := 500000 / STABLE_CLOCK_PERIOD
WAIT_1us_cycles	integer := 1000 / STABLE_CLOCK_PERIOD
WAIT_1us	integer := WAIT_1us_cycles+ 10
MAX_RETRIES	integer := 2 ** RETRY_COUNTER_BITWIDTH- 1
MAX_WAIT_BYPASS	integer := 45824

Types
TxRstFsmType	( INIT , ASSERT_ALL_RESETS , RELEASE_PLL_RESET , RELEASE_MMCM_RESET , WAIT_RESET_DONE , DO_PHASE_ALIGNMENT , RESET_FSM_DONE )

Signals
tx_state	TxRstFsmType := INIT
soft_reset_sync	std_logic
init_wait_count	integer range 0 to WAIT_MAX := 0
init_wait_done	std_logic := ' 0 '
pll_reset_asserted	std_logic := ' 0 '
tx_fsm_reset_done_int	std_logic := ' 0 '
tx_fsm_reset_done_int_s2	std_logic := ' 0 '
tx_fsm_reset_done_int_s3	std_logic := ' 0 '
txresetdone_s2	std_logic := ' 0 '
txresetdone_s3	std_logic := ' 0 '
retry_counter_int	integer range 0 to MAX_RETRIES
time_out_counter	integer range 0 to WAIT_TIMEOUT_2ms := 0
count_1us	integer range 0 to WAIT_1us := 0
reset_time_out	std_logic := ' 0 '
count_1us_done	std_logic := ' 0 '
time_out_2ms	std_logic := ' 0 '
time_tlock_max	std_logic := ' 0 '
time_out_500us	std_logic := ' 0 '
mmcm_lock_count	integer range 0 to MMCM_LOCK_CNT_MAX- 1 := 0
mmcm_lock_int	std_logic := ' 0 '
mmcm_lock_i	std_logic := ' 0 '
mmcm_lock_reclocked	std_logic := ' 0 '
run_phase_alignment_int	std_logic := ' 0 '
run_phase_alignment_int_s2	std_logic := ' 0 '
run_phase_alignment_int_s3	std_logic := ' 0 '
wait_bypass_count	integer range 0 to MAX_WAIT_BYPASS- 1
time_out_wait_bypass	std_logic := ' 0 '
time_out_wait_bypass_s2	std_logic := ' 0 '
time_out_wait_bypass_s3	std_logic := ' 0 '
txuserrdy_i	std_logic := ' 0 '
refclk_lost	std_logic
gttxreset_i	std_logic := ' 0 '
txpmaresetdone_i	std_logic := ' 0 '
txpmaresetdone_sync	std_logic
pll0lock_sync	std_logic := ' 0 '
pll1lock_sync	std_logic := ' 0 '
pll0lock_prev	std_logic := ' 0 '
pll1lock_prev	std_logic := ' 0 '
pll0lock_ris_edge	std_logic := ' 0 '
pll1lock_ris_edge	std_logic := ' 0 '

Instantiations
sync_txuserrdy	Synchronizer <Entity Synchronizer>
sync_pmaresetdone	Synchronizer <Entity Synchronizer>
sync_soft_reset	Synchronizer <Entity Synchronizer>
sync_run_phase_alignment_int	Synchronizer <Entity Synchronizer>
sync_tx_fsm_reset_done_int	Synchronizer <Entity Synchronizer>
sync_txresetdone	Synchronizer <Entity Synchronizer>
sync_time_out_wait_bypass	Synchronizer <Entity Synchronizer>
sync_mmcm_lock_reclocked	Synchronizer <Entity Synchronizer>
sync_pll0lock	Synchronizer <Entity Synchronizer>
sync_pll1lock	Synchronizer <Entity Synchronizer>

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The documentation for this design unit was generated from the following file:

• xilinx/7Series/gtp7/rtl/Gtp7TxRst.vhd