Gth7RxRstSeq.Behavioral Architecture Reference

Architecture >> Gth7RxRstSeq::Behavioral

Processes
PROCESS_401	( DRPCLK )
PROCESS_402	( DRPCLK )
PROCESS_403	( DRPRDY , gtrxreset_ss , pmarstdone_fall_edge , state )
PROCESS_404	( DRPDO , DRPRDY , flag , gtrxreset_ss , original_rd_data , rd_data , state )
PROCESS_405	( DRPCLK )

Types
StateType	( IDLE , DRP_RD , WAIT_RD_DATA , WR_16 , WAIT_WR_DONE1 , WAIT_PMARESET , WR_20 , WAIT_WR_DONE2 )

Signals
state	StateType := IDLE
next_state	StateType := IDLE
gtrxreset_s	std_logic
gtrxreset_ss	std_logic
rxpmaresetdone_ss	std_logic
rxpmaresetdone_sss	std_logic
rd_data	std_logic_vector ( 15 downto 0 )
next_rd_data	std_logic_vector ( 15 downto 0 )
original_rd_data	std_logic_vector ( 15 downto 0 )
pmarstdone_fall_edge	std_logic
gtrxreset_i	std_logic
flag	std_logic := ' 0 '
gtrxreset_o	std_logic
drpen_o	std_logic
drpwe_o	std_logic
drpaddr_o	std_logic_vector ( 8 downto 0 )
drpdi_o	std_logic_vector ( 15 downto 0 )
drp_op_done_o	std_logic
RST	std_logic
GTRXRESET	std_logic

Instantiations
sync_rxpmaresetdone	Synchronizer <Entity Synchronizer>
sync_rst	RstSync <Entity RstSync>
sync_gtrxreset	RstSync <Entity RstSync>

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The documentation for this design unit was generated from the following file:

• xilinx/7Series/gth7/rtl/Gth7RxRstSeq.vhd