GtRxAlignCheck.rtl Architecture Reference

Architecture >> GtRxAlignCheck::rtl

Processes
comb	( ack , axilRst , r , refClkFreq , resetDone , resetErr , resetIn , rxClkFreq , sAxilReadMaster , sAxilWriteMaster , txClkFreq )
seq	( axilClk )

Constants
COMMA_ALIGN_LATENCY_OFFSET_C	slv ( 31 downto 0 ) := ite ( ( GT_TYPE_G = " GTHE3 " ) , x " 0000_0540 " , x " 0000_0940 " )
COMMA_ALIGN_LATENCY_ADDR_C	slv ( 31 downto 0 ) := ( DRP_ADDR_G+ COMMA_ALIGN_LATENCY_OFFSET_C )
REG_INIT_C	RegType := ( locked = > ' 0 ' , rst = > ' 1 ' , rstRetryCnt = > ' 0 ' , override = > toSl ( SIMULATION_G ) , rstlen = > toSlv ( 3 , 4 ) , rstcnt = > toSlv ( 0 , 4 ) , retryCnt = > toSlv ( 0 , 16 ) , tgt = > toSlv ( LOCK_VALUE_G , 7 ) , mask = > toSlv ( MASK_VALUE_G , 7 ) , last = > toSlv ( 0 , 16 ) , sample = > ( others = > ( others = > ' 0 ' ) ) , sAxilWriteSlave = > AXI_LITE_WRITE_SLAVE_INIT_C , sAxilReadSlave = > AXI_LITE_READ_SLAVE_INIT_C , req = > AXI_LITE_REQ_INIT_C , state = > READ_S )

Types
StateType	( RESET_S , READ_S , ACK_S , LOCKED_S )

Signals
r	RegType := REG_INIT_C
rin	RegType
ack	AxiLiteAckType
txClkFreq	slv ( 31 downto 0 )
rxClkFreq	slv ( 31 downto 0 )
refClkFreq	slv ( 31 downto 0 )

Records
RegType

Instantiations
u_refclkfreq	SyncClockFreq <Entity SyncClockFreq>
u_txclkfreq	SyncClockFreq <Entity SyncClockFreq>
u_rxclkfreq	SyncClockFreq <Entity SyncClockFreq>
u_axilitemaster	AxiLiteMaster <Entity AxiLiteMaster>

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The documentation for this design unit was generated from the following file:

• xilinx/general/rtl/GtRxAlignCheck.vhd