GigEthReg.rtl Architecture Reference

Architecture >> GigEthReg::rtl

Processes
PROCESS_222	( localMacSync , wdtRst )
comb	( axiReadMaster , axiWriteMaster , cntOut , localMacSync , r , rst , status , statusOut , wdtRst )
seq	( clk )

Constants
STATUS_SIZE_C	positive := 32
REG_INIT_C	RegType := ( hardRst = > ' 0 ' , cntRst = > ' 1 ' , rollOverEn = > ( others = > ' 0 ' ) , config = > GIG_ETH_CONFIG_INIT_C , axiReadSlave = > AXI_LITE_READ_SLAVE_INIT_C , axiWriteSlave = > AXI_LITE_WRITE_SLAVE_INIT_C )

Signals
r	RegType := REG_INIT_C
rin	RegType
statusOut	slv ( STATUS_SIZE_C- 1 downto 0 )
cntOut	SlVectorArray ( STATUS_SIZE_C- 1 downto 0 , 31 downto 0 )
localMacSync	slv ( 47 downto 0 )
wdtRst	sl

Records
RegType

Instantiations
u_watchdogrst	WatchDogRst <Entity WatchDogRst>
sync_config	SynchronizerVector <Entity SynchronizerVector>
syncstatusvec_inst	SyncStatusVector <Entity SyncStatusVector>

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The documentation for this design unit was generated from the following file:

• ethernet/GigEthCore/core/rtl/GigEthReg.vhd