FwftCntTb.testbed Architecture Reference

Architecture >> FwftCntTb::testbed

Processes
seq	( clk )
PROCESS_35	( failed , passed )
seq	( clk )
PROCESS_109	( failed , passed )

Constants
CLK_PERIOD_G	time := 10 ns
TPD_G	time := CLK_PERIOD_G/ 4
CONFIG_TEST_SIZE_C	natural := 2 ** 3

Signals
clk	sl := ' 0 '
rst	sl := ' 1 '
passedVec	slv ( CONFIG_TEST_SIZE_C- 1 downto 0 ) := ( others = > ' 0 ' )
failedVec	slv ( CONFIG_TEST_SIZE_C- 1 downto 0 ) := ( others = > ' 0 ' )
passed	sl := ' 0 '
failed	sl := ' 0 '

Instantiations
u_clkrst	ClkRst <Entity ClkRst>
u_submodule	FwftCntTbSubModule <Entity FwftCntTbSubModule>
u_clkrst	ClkRst <Entity ClkRst>
u_submodule	FwftCntTbSubModule <Entity FwftCntTbSubModule>

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The documentation for this design unit was generated from the following files:

• base/fifo/tb/FwftCntTb.vhd
• build/SRC_VHDL/surf/FwftCntTb.vhd