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FirFilterSingleChannelTestWrapper.rtl Architecture Reference
Architecture >> FirFilterSingleChannelTestWrapper::rtl

Signals

axilClkSig  sl
axilRstSig  sl
axilReadMaster  AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
axilReadSlave  AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_INIT_C
axilWriteMaster  AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
axilWriteSlave  AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_INIT_C

Instantiations

u_axil  SlaveAxiLiteIpIntegrator <Entity SlaveAxiLiteIpIntegrator>
u_dut  FirFilterSingleChannel <Entity FirFilterSingleChannel>

The documentation for this design unit was generated from the following file: