Architecture >> FirAverage::rtl

Constants
BIT_GROWTH_C	integer := log2 ( FIR_LEN_G )
DIN_DELAY_C	*integer := FIR_LEN_G ILEAVE_CHAN_G**
DIN_DELAY_STYLE_C	string := ite ( DIN_DELAY_C> BRAM_THRESH_G , " block " , " srl_reg " )
ACCUM_DELAY_C	integer := ILEAVE_CHAN_G- 1
ACCUM_DELAY_STYLE_C	string := ite ( ACCUM_DELAY_C> BRAM_THRESH_G , " block " , " srl_reg " )
TOT_LATENCY_C	integer := 1 + ite ( REG_IN_G , 1 , 0 ) + ite ( REG_OUT_G , 1 , 0 )
INT_OVERFLOW_STYLE_C	fixed_overflow_style_type := fixed_wrap
INT_ROUNDING_STYLE_C	fixed_round_style_type := fixed_truncate
REG_INIT_C	RegType := ( din = > ( others = > ' 0 ' ) , dout = > ( others = > ' 0 ' ) )

Signals
r	RegType := REG_INIT_C
rin	RegType
dinInt	sfixed ( din )
dinIntDelay	sfixed ( din )
doutInt	sfixed ( dout )
filtOut	sfixed ( din ' high+ BIT_GROWTH_C downto din ' low )
filtDly	sfixed ( din ' high+ BIT_GROWTH_C downto din ' low )
filtOutShift	sfixed ( din ' high downto din ' low- BIT_GROWTH_C )
userDelayIn	slv ( userIn ' length downto 0 )
userDelayOut	slv ( userIn ' length downto 0 )

Records
RegType

Instantiations
u_user_delay	SlvFixedDelay <Entity SlvFixedDelay>
u_din_delay	sfixedDelay <Entity sfixedDelay>
u_accum_delay	sfixedDelay <Entity sfixedDelay>
u_add_sub	add3 <Entity add3>

The documentation for this design unit was generated from the following file:

Processes

Constants