FirAverage Entity Reference

Inheritance diagram for FirAverage:

Collaboration diagram for FirAverage:

Entities
FirAverage.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
fixed_pkg
fixed_float_types
StdRtlPkg	Package <StdRtlPkg>

Generics
TPD_G	time := 1 ns
XIL_DEVICE_G	string := " ULTRASCALE_PLUS "
USE_CSA3_G	boolean := false
BRAM_THRESH_G	integer := 256
FIR_LEN_G	integer := 16
ILEAVE_CHAN_G	integer := 1
USER_WIDTH_G	integer := 0
REG_IN_G	boolean := true
REG_OUT_G	boolean := true

Ports
clk	in	sl
rst	in	sl := ' 0 '
validIn	in	sl := ' 0 '
userIn	in	slv ( USER_WIDTH_G- 1 downto 0 ) := ( others = > ' 0 ' )
din	in	sfixed
validOut	out	sl
userOut	out	slv ( USER_WIDTH_G- 1 downto 0 )
dout	out	sfixed

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The documentation for this design unit was generated from the following file:

• dsp/xilinx/fixed/FirAverage.vhd