add3 Entity Reference

Inheritance diagram for add3:

Collaboration diagram for add3:

Entities
add3.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
numeric_std
fixed_pkg
fixed_float_types
StdRtlPkg	Package <StdRtlPkg>

Generics
TPD_G	time := 1 ns
XIL_DEVICE_G	string := " ULTRASCALE_PLUS "
USE_CSA3_G	boolean := false
REG_IN_G	boolean := false
REG_OUT_G	boolean := true
NEGATIVE_A_G	boolean := false
NEGATIVE_B_G	boolean := false
EXTRA_MSB_G	integer := 2

Ports
clk	in	sl
rst	in	sl := ' 0 '
a	in	sfixed
b	in	sfixed
c	in	sfixed
y	out	sfixed

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The documentation for this design unit was generated from the following file:

• dsp/xilinx/fixed/Add3.vhd