add3.rtl Architecture Reference

Architecture >> add3::rtl

Processes
comb	( a , b , c , r )
seq	( clk )

Constants
INT_OVERFLOW_STYLE_C	fixed_overflow_style_type := fixed_wrap
INT_ROUNDING_STYLE_C	fixed_round_style_type := fixed_truncate
HIGH_ARRAY_C	IntegerArray ( 2 downto 0 ) := ( 0 = > a ' high , 1 = > b ' high , 2 = > c ' high )
LOW_ARRAY_C	IntegerArray ( 2 downto 0 ) := ( 0 = > a ' low , 1 = > b ' low , 2 = > c ' low )
HIGH_BIT_C	integer := maximum ( HIGH_ARRAY_C ) + EXTRA_MSB_G
LOW_BIT_C	integer := minimum ( LOW_ARRAY_C )
REG_INIT_C	RegType := ( a = > ( others = > ' 0 ' ) , b = > ( others = > ' 0 ' ) , c = > ( others = > ' 0 ' ) , sum = > ( others = > ' 0 ' ) )

Signals
r	RegType := REG_INIT_C
rin	RegType

Records
RegType

Instantiations
csa3	csa3 <Entity csa3>

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The documentation for this design unit was generated from the following file:

• dsp/fixed/Add3.vhd