Fifo.rtl Architecture Reference

Architecture >> Fifo::rtl

Constants
INIT_C	slv ( DATA_WIDTH_G- 1 downto 0 ) := ite ( INIT_G = " 0 " , slvZero ( DATA_WIDTH_G ) , INIT_G )

Signals
data_count	slv ( ADDR_WIDTH_G- 1 downto 0 ) := ( others = > ' 0 ' )

Instantiations
u_xpm	FifoXpm <Entity FifoXpm>
u_mf	FifoAlteraMf <Entity FifoAlteraMf>
fifoasync_inst	FifoAsync <Entity FifoAsync>
fifosync_inst	FifoSync <Entity FifoSync>
u_xpm	FifoXpm <Entity FifoXpm>
u_mf	FifoAlteraMf <Entity FifoAlteraMf>
fifoasync_inst	FifoAsync <Entity FifoAsync>
fifosync_inst	FifoSync <Entity FifoSync>

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The documentation for this design unit was generated from the following files:

• base/fifo/rtl/Fifo.vhd
• build/SRC_VHDL/surf/Fifo.vhd