FifoAlteraMf Entity Reference

Inheritance diagram for FifoAlteraMf:

Collaboration diagram for FifoAlteraMf:

Entities
FifoAlteraMf.mapping	architecture

Libraries
ieee
surf
altera_mf

Use Clauses
std_logic_1164
std_logic_unsigned
std_logic_arith
StdRtlPkg	Package <StdRtlPkg>
all

Generics
TPD_G	time := 1 ns
RST_POLARITY_G	sl := ' 1 '
RST_ASYNC_G	boolean := false
FWFT_EN_G	boolean := false
GEN_SYNC_FIFO_G	boolean := false
MEMORY_TYPE_G	string := " auto "
SYNC_STAGES_G	positive := 3
PIPE_STAGES_G	natural := 0
DATA_WIDTH_G	positive := 18
ADDR_WIDTH_G	positive := 10
FULL_THRES_G	positive := 16
EMPTY_THRES_G	positive := 16

Ports
rst	in	sl
wr_clk	in	sl
wr_en	in	sl
din	in	slv ( DATA_WIDTH_G- 1 downto 0 )
wr_data_count	out	slv ( ADDR_WIDTH_G- 1 downto 0 )
wr_ack	out	sl
overflow	out	sl
prog_full	out	sl
almost_full	out	sl
full	out	sl
not_full	out	sl
rd_clk	in	sl
rd_en	in	sl
dout	out	slv ( DATA_WIDTH_G- 1 downto 0 )
rd_data_count	out	slv ( ADDR_WIDTH_G- 1 downto 0 )
valid	out	sl
underflow	out	sl
prog_empty	out	sl
almost_empty	out	sl
empty	out	sl

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The documentation for this design unit was generated from the following files:

• base/fifo/rtl/altera/FifoAlteraMf.vhd
• base/fifo/rtl/dummy/FifoAlteraMfDummy.vhd
• build/SRC_VHDL/surf/FifoAlteraMfDummy.vhd