FifoAlteraMf.mapping Architecture Reference

Architecture >> FifoAlteraMf::mapping

Processes
PROCESS_30	( fifoEmpty , fifoFull , rdCount , wrCount )

Constants
FWFT_EN_C	string := ite ( FWFT_EN_G , " ON " , " OFF " )

Signals
reset	sl
sRdEn	sl
sValid	sl
dataOut	slv ( DATA_WIDTH_G- 1 downto 0 )
fifoFull	sl
fifoEmpty	sl
wrCount	slv ( ADDR_WIDTH_G- 1 downto 0 )
rdCount	slv ( ADDR_WIDTH_G- 1 downto 0 )

Instantiations
u_dcfifo	dcfifo
u_scfifo	scfifo
u_pipeline	FifoOutputPipeline <Entity FifoOutputPipeline>

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The documentation for this design unit was generated from the following file:

• base/fifo/rtl/altera/FifoAlteraMf.vhd