FifoMux.rtl Architecture Reference

Architecture >> FifoMux::rtl

Processes
wrComb	( din , wrR , wr_en )
wrSeq	( rst , wr_clk )
rdComb	( fifo_dout , fifo_empty , fifo_valid , rdR , rd_en )
rdSeq	( rdRst , rd_clk )
wrComb	( din , wrR , wr_en )
wrSeq	( rst , wr_clk )
rdComb	( fifo_dout , fifo_empty , fifo_valid , rdR , rd_en )
rdSeq	( rdRst , rd_clk )

Constants
FIFO_DATA_WIDTH_C	integer := ite ( WR_DATA_WIDTH_G> RD_DATA_WIDTH_G , WR_DATA_WIDTH_G , RD_DATA_WIDTH_G )
WR_LOGIC_EN_C	boolean := ( WR_DATA_WIDTH_G< RD_DATA_WIDTH_G )
WR_SIZE_C	integer := ite ( WR_LOGIC_EN_C , RD_DATA_WIDTH_G/ WR_DATA_WIDTH_G , 1 )
WR_REG_INIT_C	WrRegType := ( count = > ( others = > ' 0 ' ) , wrData = > ( others = > ( others = > ' 0 ' ) ) , wrEn = > ' 0 ' )
RD_LOGIC_EN_C	boolean := ( RD_DATA_WIDTH_G< WR_DATA_WIDTH_G )
RD_SIZE_C	integer := ite ( RD_LOGIC_EN_C , WR_DATA_WIDTH_G/ RD_DATA_WIDTH_G , 1 )
RD_REG_INIT_C	RdRegType := ( count = > ( others = > ' 0 ' ) )

Types
WrDataArray	( 0 to WR_SIZE_C- 1 ) slv ( WR_DATA_WIDTH_G- 1 downto 0 )
RdDataArray	( 0 to RD_SIZE_C- 1 ) slv ( RD_DATA_WIDTH_G- 1 downto 0 )

Signals
wrR	WrRegType := WR_REG_INIT_C
wrRin	WrRegType := WR_REG_INIT_C
fifo_din	slv ( FIFO_DATA_WIDTH_C- 1 downto 0 )
fifo_wr_en	sl
wrRst	sl
rdR	RdRegType := RD_REG_INIT_C
rdRin	RdRegType := RD_REG_INIT_C
fifo_dout	slv ( FIFO_DATA_WIDTH_C- 1 downto 0 )
fifo_rd_data	slv ( RD_DATA_WIDTH_G- 1 downto 0 )
fifo_valid	sl
fifo_rd_en	sl
fifo_empty	sl
rdRst	sl

Records
WrRegType
RdRegType

Instantiations
rstsync_rdrst	RstSync <Entity RstSync>
fifocascade_inst	FifoCascade <Entity FifoCascade>
rstsync_rdrst	RstSync <Entity RstSync>
fifocascade_inst	FifoCascade <Entity FifoCascade>

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The documentation for this design unit was generated from the following files:

• base/fifo/rtl/FifoMux.vhd
• build/SRC_VHDL/surf/FifoMux.vhd