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FifoFwftTb.testbed Architecture Reference
Architecture >> FifoFwftTb::testbed

Processes

PROCESS_32  ( failed , passed )
PROCESS_106  ( failed , passed )

Constants

TPD_C  time := 1 ns
WRITE_CLK_PERIOD_C  time := 5 ns
READ_CLK_PERIOD_C  time := 4 ns
CONFIG_TEST_SIZE_C  natural := 15
SIM_CONFIG_C  SimConfigArray ( 0 to 15 ) := ( 0 = > ( PIPE_STAGES_G = > 0 , GEN_SYNC_FIFO_G = > false , MEMORY_TYPE_G = > " distributed " ) , 1 = > ( PIPE_STAGES_G = > 0 , GEN_SYNC_FIFO_G = > false , MEMORY_TYPE_G = > " distributed " ) , 2 = > ( PIPE_STAGES_G = > 0 , GEN_SYNC_FIFO_G = > false , MEMORY_TYPE_G = > " block " ) , 3 = > ( PIPE_STAGES_G = > 0 , GEN_SYNC_FIFO_G = > false , MEMORY_TYPE_G = > " block " ) , 4 = > ( PIPE_STAGES_G = > 0 , GEN_SYNC_FIFO_G = > true , MEMORY_TYPE_G = > " distributed " ) , 5 = > ( PIPE_STAGES_G = > 0 , GEN_SYNC_FIFO_G = > true , MEMORY_TYPE_G = > " distributed " ) , 6 = > ( PIPE_STAGES_G = > 0 , GEN_SYNC_FIFO_G = > true , MEMORY_TYPE_G = > " block " ) , 7 = > ( PIPE_STAGES_G = > 0 , GEN_SYNC_FIFO_G = > true , MEMORY_TYPE_G = > " block " ) , 8 = > ( PIPE_STAGES_G = > 1 , GEN_SYNC_FIFO_G = > false , MEMORY_TYPE_G = > " distributed " ) , 9 = > ( PIPE_STAGES_G = > 1 , GEN_SYNC_FIFO_G = > false , MEMORY_TYPE_G = > " distributed " ) , 10 = > ( PIPE_STAGES_G = > 1 , GEN_SYNC_FIFO_G = > false , MEMORY_TYPE_G = > " block " ) , 11 = > ( PIPE_STAGES_G = > 1 , GEN_SYNC_FIFO_G = > false , MEMORY_TYPE_G = > " block " ) , 12 = > ( PIPE_STAGES_G = > 1 , GEN_SYNC_FIFO_G = > true , MEMORY_TYPE_G = > " distributed " ) , 13 = > ( PIPE_STAGES_G = > 1 , GEN_SYNC_FIFO_G = > true , MEMORY_TYPE_G = > " distributed " ) , 14 = > ( PIPE_STAGES_G = > 1 , GEN_SYNC_FIFO_G = > true , MEMORY_TYPE_G = > " block " ) , 15 = > ( PIPE_STAGES_G = > 1 , GEN_SYNC_FIFO_G = > true , MEMORY_TYPE_G = > " block " ) )

Subtypes

SimConfigArray  array ( natural range <> ) of SimConfigType

Signals

wrClk  sl
rst  sl
rdClk  sl
failed  slv ( 0 to CONFIG_TEST_SIZE_C ) := ( others = > ' 0 ' )
passed  slv ( 0 to CONFIG_TEST_SIZE_C ) := ( others = > ' 0 ' )
subRdClk  slv ( 0 to CONFIG_TEST_SIZE_C ) := ( others = > ' 0 ' )

Records

SimConfigType 

Instantiations

clkrst_write  ClkRst <Entity ClkRst>
clkrst_read  ClkRst <Entity ClkRst>
fifotbsubmodule_inst  FifoTbSubModule <Entity FifoTbSubModule>
clkrst_write  ClkRst <Entity ClkRst>
clkrst_read  ClkRst <Entity ClkRst>
fifotbsubmodule_inst  FifoTbSubModule <Entity FifoTbSubModule>
The documentation for this design unit was generated from the following files: