FifoTbSubModule Entity Reference

Inheritance diagram for FifoTbSubModule:

Collaboration diagram for FifoTbSubModule:

Entities
FifoTbSubModule.mapping	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned
StdRtlPkg	Package <StdRtlPkg>

Generics
TPD_G	time := 1 ns
GEN_SYNC_FIFO_G	boolean := false
MEMORY_TYPE_G	string := " block "
PIPE_STAGES_G	natural range 0 to 16 := 0

Ports
rst	in	sl
wrClk	in	sl
rdClk	in	sl
passed	out	sl := ' 0 '
failed	out	sl := ' 0 '

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The documentation for this design unit was generated from the following files:

• base/fifo/tb/FifoFwftTbSubModule.vhd
• build/SRC_VHDL/surf/FifoFwftTbSubModule.vhd