FifoTbSubModule.mapping Architecture Reference

Architecture >> FifoTbSubModule::mapping

Processes
PROCESS_33	( wrClk )
PROCESS_34	( rdClk )
PROCESS_107	( wrClk )
PROCESS_108	( rdClk )

Signals
wrEn	sl := ' 0 '
aFull	sl := ' 0 '
valid	sl := ' 0 '
rdE	sl := ' 0 '
passedDet	sl := ' 0 '
failedDet	sl := ' 0 '
ready	sl := ' 0 '
readDelay	slv ( 4 downto 0 ) := ( others = > ' 0 ' )
writeDelay	slv ( 4 downto 0 ) := ( others = > ' 0 ' )
din	slv ( 15 downto 0 ) := ( others = > ' 0 ' )
dout	slv ( 15 downto 0 ) := ( others = > ' 0 ' )
check	slv ( 15 downto 0 ) := ( others = > ' 0 ' )

Instantiations
fifo_inst	Fifo <Entity Fifo>
fifo_inst	Fifo <Entity Fifo>

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The documentation for this design unit was generated from the following files:

• base/fifo/tb/FifoFwftTbSubModule.vhd
• build/SRC_VHDL/surf/FifoFwftTbSubModule.vhd