Architecture >> EthMacTxCsum::rtl

Processes
comb	( eofeDet , ethRst , fragDet , ipCsumEn , ipv4Csum , ipv4Det , ipv4Len , mMaster , protCsum , protLen , r , roce , rxMaster , sSlave , tcpCsumEn , tcpDet , tranPause , tranValid , txSlave , udpCsumEn , udpDet )
seq	( ethClk )

Constants
MAX_FRAME_SIZE_C	natural := ite ( JUMBO_G , 9000 , 1500 )
ROCEV2_CRC32_BYTE_WIDTH_C	natural := 4
REG_INIT_C	RegType := ( tranWr = > ' 0 ' , fragDet = > ( others = > ' 0 ' ) , eofeDet = > ( others = > ' 0 ' ) , ipv4Det = > ( others = > ' 0 ' ) , udpDet = > ( others = > ' 0 ' ) , tcpDet = > ( others = > ' 0 ' ) , tcpFlag = > ' 0 ' , ipv4Len = > ( others = > ( others = > ' 0 ' ) ) , ipv4Csum = > ( others = > ' 0 ' ) , protLen = > ( others = > ( others = > ' 0 ' ) ) , protCsum = > ( others = > ' 0 ' ) , ipv4Hdr = > ( others = > ( others = > ' 0 ' ) ) , calc = > ( others = > ETH_MAC_CSUM_ACCUM_INIT_C ) , len = > ( others = > ' 0 ' ) , tKeep = > ( others = > ' 0 ' ) , tData = > ( others = > ' 0 ' ) , tranRd = > ' 0 ' , mvCnt = > 0 , dbg = > ( others = > ' 0 ' ) , roce = > ( others = > ' 0 ' ) , rxSlave = > AXI_STREAM_SLAVE_INIT_C , txMaster = > AXI_STREAM_MASTER_INIT_C , mSlave = > AXI_STREAM_SLAVE_INIT_C , sMaster = > AXI_STREAM_MASTER_INIT_C , state = > IDLE_S )

Types
StateType	( IDLE_S , IPV4_HDR0_S , IPV4_HDR1_S , MOVE_S , BLOWOFF_S )

Records
RegType

Instantiations
u_rxpipeline	AxiStreamPipeline <Entity AxiStreamPipeline>
fifo_cache	AxiStreamFifoV2 <Entity AxiStreamFifoV2>
fifo_trans	Fifo <Entity Fifo>
u_txpipeline	AxiStreamPipeline <Entity AxiStreamPipeline>

The documentation for this design unit was generated from the following file:

Processes

Constants