Architecture >> EthMacTb::testbed

Processes
comb	( ethStatus , r , rst , rxMaster , txSlave )
seq	( clk )

Constants
CLK_PERIOD_C	time := 10 ns
TPD_G	time := ( CLK_PERIOD_C/ 4 )
AXIS_CONFIG_C	AxiStreamConfigType := ssiAxiStreamConfig ( 1 )
PRESET_SIZE_G	slv ( 7 downto 0 ) := toSlv ( 11 , 8 )
REG_INIT_C	RegType := ( txMaster = > AXI_STREAM_MASTER_INIT_C , txSize = > PRESET_SIZE_G , txCnt = > ( others = > ' 0 ' ) , rxSlave = > AXI_STREAM_SLAVE_INIT_C , rxSize = > PRESET_SIZE_G , rxCnt = > ( others = > ' 0 ' ) , errorDet = > ( others = > ' 0 ' ) , errorDetDly = > ' 0 ' )

Signals
r	RegType := REG_INIT_C
rin	RegType
clk	sl := ' 0 '
rst	sl := ' 0 '
phyReady	sl := ' 0 '
txMaster	AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C
txSlave	AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C
rxMaster	AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C
rxSlave	AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C
ethStatus	EthMacStatusType := ETH_MAC_STATUS_INIT_C
ethConfig	EthMacConfigType := ETH_MAC_CONFIG_INIT_C
phyD	slv ( 63 downto 0 ) := ( others = > ' 0 ' )
phyC	slv ( 7 downto 0 ) := ( others = > ' 0 ' )

Records
RegType

The documentation for this design unit was generated from the following file:

Processes

Constants