EthMacRxFifo.rtl Architecture Reference

Architecture >> EthMacRxFifo::rtl

Processes
comb	( bypDrop , pauseThresh , phyReady , primDrop , r , sRst )
seq	( sClk )

Constants
MAX_THRESH_SLV_C	slv ( FIFO_ADDR_WIDTH_G- 1 downto 0 ) := ( others = > ' 1 ' )
VALID_THOLD_C	natural := ite ( DROP_ERR_PKT_G , 0 , 1 )
REG_INIT_C	RegType := ( rxFifoDrop = > ' 0 ' , fifoPauseThresh = > MAX_THRESH_SLV_C )

Signals
r	RegType := REG_INIT_C
rin	RegType
primDrop	sl := ' 0 '
bypDrop	sl := ' 0 '

Records
RegType

Instantiations
u_fifo	SsiFifo <Entity SsiFifo>
u_fifo	SsiFifo <Entity SsiFifo>

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The documentation for this design unit was generated from the following file:

• ethernet/EthMacCore/rtl/EthMacRxFifo.vhd