EthMacRxFifo Entity Reference

Inheritance diagram for EthMacRxFifo:

Collaboration diagram for EthMacRxFifo:

Entities
EthMacRxFifo.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_unsigned
std_logic_arith
StdRtlPkg	Package <StdRtlPkg>
AxiStreamPkg	Package <AxiStreamPkg>
EthMacPkg	Package <EthMacPkg>

Generics
TPD_G	time := 1 ns
RST_POLARITY_G	sl := ' 1 '
RST_ASYNC_G	boolean := false
SYNTH_MODE_G	string := " inferred "
MEMORY_TYPE_G	string := " block "
DROP_ERR_PKT_G	boolean := true
INT_PIPE_STAGES_G	natural := 1
PIPE_STAGES_G	natural := 1
FIFO_ADDR_WIDTH_G	positive range 9 to 16 := 11
PRIM_COMMON_CLK_G	boolean := false
PRIM_CONFIG_G	AxiStreamConfigType := INT_EMAC_AXIS_CONFIG_C
BYP_EN_G	boolean := false
BYP_COMMON_CLK_G	boolean := false
BYP_CONFIG_G	AxiStreamConfigType := INT_EMAC_AXIS_CONFIG_C

Ports
sClk	in	sl
sRst	in	sl
phyReady	in	sl
rxFifoDrop	out	sl
pauseThresh	in	slv ( 15 downto 0 )
mPrimClk	in	sl
mPrimRst	in	sl
sPrimMaster	in	AxiStreamMasterType
sPrimCtrl	out	AxiStreamCtrlType
mPrimMaster	out	AxiStreamMasterType
mPrimSlave	in	AxiStreamSlaveType
mBypClk	in	sl
mBypRst	in	sl
sBypMaster	in	AxiStreamMasterType
sBypCtrl	out	AxiStreamCtrlType
mBypMaster	out	AxiStreamMasterType
mBypSlave	in	AxiStreamSlaveType

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The documentation for this design unit was generated from the following file:

• ethernet/EthMacCore/rtl/EthMacRxFifo.vhd