EthMacFastTb.testbed Architecture Reference

Architecture >> EthMacFastTb::testbed

Processes
p_DataGen

Constants
CLK_PERIOD_C	time := 10 ns
TPD_G	time := ( CLK_PERIOD_C/ 4 )

Signals
clk	sl := ' 0 '
rst	sl := ' 1 '
phyReady	sl := ' 0 '
txMaster	AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C
txSlave	AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C
rxMaster	AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C
rxSlave	AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C
ethStatus	EthMacStatusType := ETH_MAC_STATUS_INIT_C
ethConfig	EthMacConfigType := ETH_MAC_CONFIG_INIT_C
phyRxD	slv ( 63 downto 0 ) := ( others = > ' 0 ' )
phyRxC	slv ( 7 downto 0 ) := ( others = > ' 0 ' )
phyTxD	slv ( 63 downto 0 ) := ( others = > ' 0 ' )
phyTxC	slv ( 7 downto 0 ) := ( others = > ' 0 ' )

Instantiations
clkrst_inst	ClkRst <Entity ClkRst>
u_mac	EthMacTop <Entity EthMacTop>

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The documentation for this design unit was generated from the following file:

• ethernet/EthMacCore/tb/EthMacFastTb.vhd