DspSquareDiffMult.rtl Architecture Reference

Architecture >> DspSquareDiffMult::rtl

Processes
comb	( ain , bin , ibValid , r , rst , tReady )
seq	( clk , rst )
comb	( ain , bin , ibValid , r , rst , tReady )
seq	( clk , rst )

Constants
REG_INIT_C	RegType := ( ibReady = > ' 0 ' , tReady = > ' 0 ' , tValid = > ( others = > ' 0 ' ) , diff = > ( others = > ' 0 ' ) , p = > ( others = > ' 0 ' ) )

Signals
r	RegType := REG_INIT_C
rin	RegType
tReady	slv ( 1 downto 0 )
p	slv ( 2 * WIDTH_G+ 1 downto 0 )

Attributes
use_dsp	string
use_dsp	signal is USE_DSP_G

Records
RegType

Instantiations
u_pipe	FifoOutputPipeline <Entity FifoOutputPipeline>
u_pipe	FifoOutputPipeline <Entity FifoOutputPipeline>

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/DspSquareDiffMult.vhd
• dsp/generic/fixed/DspSquareDiffMult.vhd