DspSquareDiffMult Entity Reference

Inheritance diagram for DspSquareDiffMult:

Collaboration diagram for DspSquareDiffMult:

Entities
DspSquareDiffMult.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
numeric_std
StdRtlPkg	Package <StdRtlPkg>

Generics
TPD_G	time := 1 ns
RST_POLARITY_G	sl := ' 1 '
RST_ASYNC_G	boolean := false
USE_DSP_G	string := " yes "
PIPE_STAGES_G	natural range 0 to 1 := 0
WIDTH_G	positive := 16

Ports
clk	in	sl
rst	in	sl := not ( RST_POLARITY_G )
ibValid	in	sl := ' 1 '
ibReady	out	sl
ain	in	slv ( WIDTH_G- 1 downto 0 )
bin	in	slv ( WIDTH_G- 1 downto 0 )
obValid	out	sl
obReady	in	sl := ' 1 '
pOut	out	slv ( 2 * WIDTH_G+ 1 downto 0 )

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/DspSquareDiffMult.vhd
• dsp/generic/fixed/DspSquareDiffMult.vhd