Code12b14bTb.sim Architecture Reference

Architecture >> Code12b14bTb::sim

Functions
boolean	isKCode ( d: in slv( 11 downto 0) )	[ impure ]
boolean	isKCode ( d: in slv( 11 downto 0) )	[ impure ]

Processes
main
monitor
main
monitor

Procedures
	doComb( a: in slv ( 11 downto 0 ) ak: in sl b: in slv ( 11 downto 0 ) bk: in sl )
	doComb( a: in slv ( 11 downto 0 ) ak: in sl b: in slv ( 11 downto 0 ) bk: in sl )

Constants
TPD_G	time := 1 ns
RST_POLARITY_G	sl := ' 1 '
RST_ASYNC_G	boolean := false

Signals
clk	sl
clkEn	sl := ' 1 '
rst	sl := not RST_POLARITY_G
encDispIn	slv ( 1 downto 0 )
encDataIn	slv ( 11 downto 0 ) := ( others = > ' 0 ' )
encDataKIn	sl := ' 0 '
encDataOut	slv ( 13 downto 0 )
encDispOut	slv ( 1 downto 0 )
encInvalidK	sl
started	boolean := false
run	integer := 0
lastEncDataOut	slv ( 13 downto 0 )
encDispInInt	BlockDisparityType
encDispOutInt	BlockDisparityType
encDataInString	string ( 1 to 8 )
decDataIn	slv ( 13 downto 0 )
decDispIn	slv ( 1 downto 0 ) := " 01 "
decDataOut	slv ( 11 downto 0 )
decDataKOut	sl
decDispOut	slv ( 1 downto 0 )
decCodeError	sl
decDispError	sl
dlyDataOut	slv ( 11 downto 0 )
dlyDataKOut	sl

Shared Variables
runVar	shared integer := := 0

Instantiations
u_encoder12b14b	Encoder12b14b <Entity Encoder12b14b>
u_clkrst_1	ClkRst <Entity ClkRst>
u_decoder12b14b_1	Decoder12b14b <Entity Decoder12b14b>
u_synchronizervector_1	SynchronizerVector <Entity SynchronizerVector>
u_encoder12b14b	Encoder12b14b <Entity Encoder12b14b>
u_clkrst_1	ClkRst <Entity ClkRst>
u_decoder12b14b_1	Decoder12b14b <Entity Decoder12b14b>
u_synchronizervector_1	SynchronizerVector <Entity SynchronizerVector>

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/Code12b14bTb.vhd
• protocols/line-codes/tb/Code12b14bTb.vhd