Architecture >> CoaxpressOverFiberGthUs::mapping

Constants
MON_AXIL_INDEX_C	integer := 0
DRP_AXIL_INDEX_C	integer := 1
NUM_AXIL_MASTERS_C	integer := ( 1 + NUM_LANES_G )
XBAR_CONFIG_C	AxiLiteCrossbarMasterConfigArray ( NUM_AXIL_MASTERS_C- 1 downto 0 ) := genAxiLiteConfig ( NUM_AXIL_MASTERS_C , AXIL_BASE_ADDR_G , 16 , 12 )

Signals
axilReadMasters	AxiLiteReadMasterArray ( NUM_AXIL_MASTERS_C- 1 downto 0 )
axilReadSlaves	AxiLiteReadSlaveArray ( NUM_AXIL_MASTERS_C- 1 downto 0 ) := ( others = > AXI_LITE_READ_SLAVE_EMPTY_DECERR_C )
axilWriteMasters	AxiLiteWriteMasterArray ( NUM_AXIL_MASTERS_C- 1 downto 0 )
axilWriteSlaves	AxiLiteWriteSlaveArray ( NUM_AXIL_MASTERS_C- 1 downto 0 ) := ( others = > AXI_LITE_WRITE_SLAVE_EMPTY_DECERR_C )
txClk	slv ( NUM_LANES_G- 1 downto 0 ) := ( others = > ' 0 ' )
txRst	slv ( NUM_LANES_G- 1 downto 0 ) := ( others = > ' 0 ' )
txLsValid	slv ( NUM_LANES_G- 1 downto 0 ) := ( others = > ' 0 ' )
txLsData	slv8Array ( NUM_LANES_G- 1 downto 0 ) := ( others = > CXP_IDLE_C ( 7 downto 0 ) )
txLsDataK	slv ( NUM_LANES_G- 1 downto 0 ) := ( others = > ' 1 ' )
txLsLaneEn	Slv4Array ( NUM_LANES_G- 1 downto 0 ) := ( others = > x " 0 " )
txLsRate	slv ( NUM_LANES_G- 1 downto 0 ) := ( others = > ' 0 ' )
txLinkUp	slv ( NUM_LANES_G- 1 downto 0 )
rxClk	slv ( NUM_LANES_G- 1 downto 0 ) := ( others = > ' 0 ' )
rxRst	slv ( NUM_LANES_G- 1 downto 0 ) := ( others = > ' 0 ' )
rxData	slv32Array ( NUM_LANES_G- 1 downto 0 ) := ( others = > CXP_IDLE_C )
rxDataK	Slv4Array ( NUM_LANES_G- 1 downto 0 ) := ( others = > CXP_IDLE_K_C )
rxDispErr	slv ( NUM_LANES_G- 1 downto 0 ) := ( others = > ' 0 ' )
rxDecErr	slv ( NUM_LANES_G- 1 downto 0 ) := ( others = > ' 0 ' )
rxLinkUp	slv ( NUM_LANES_G- 1 downto 0 ) := ( others = > ' 0 ' )

Instantiations
u_xbar	AxiLiteCrossbar <Entity AxiLiteCrossbar>
u_core	CoaXPressCore <Entity CoaXPressCore>
u_cxpof	CoaXPressOverFiberGthUsIpWrapper <Entity CoaXPressOverFiberGthUsIpWrapper>

The documentation for this design unit was generated from the following file:

Constants

Signals