CoaXPressRxLaneMux.rtl Architecture Reference

Architecture >> CoaXPressRxLaneMux::rtl

Processes
comb	( numOfLane , pipeSlave , r , rxFsmRst , rxMasters , rxRst )
seq	( rxClk )

Constants
REG_INIT_C	RegType := ( numOfLane = > ( others = > ' 0 ' ) , lane = > 0 , rxSlaves = > ( others = > AXI_STREAM_SLAVE_FORCE_C ) , pipeMaster = > AXI_STREAM_MASTER_INIT_C )

Signals
r	RegType := REG_INIT_C
rin	RegType
pipeSlave	AxiStreamSlaveType

Records
RegType

Instantiations
u_pipeline	AxiStreamPipeline <Entity AxiStreamPipeline>

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The documentation for this design unit was generated from the following file:

• protocols/coaxpress/core/rtl/CoaXPressRxLaneMux.vhd