CoaXPressRxLaneMux Entity Reference

Inheritance diagram for CoaXPressRxLaneMux:

Collaboration diagram for CoaXPressRxLaneMux:

Entities
CoaXPressRxLaneMux.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_unsigned
std_logic_arith
StdRtlPkg	Package <StdRtlPkg>
AxiStreamPkg	Package <AxiStreamPkg>

Generics
TPD_G	time := 1 ns
NUM_LANES_G	positive := 1

Ports
rxClk	in	sl
rxRst	in	sl
rxFsmRst	in	sl
numOfLane	in	slv ( 2 downto 0 )
rxMasters	in	AxiStreamMasterArray ( NUM_LANES_G- 1 downto 0 )
rxSlaves	out	AxiStreamSlaveArray ( NUM_LANES_G- 1 downto 0 )
rxMaster	out	AxiStreamMasterType
rxSlave	in	AxiStreamSlaveType

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The documentation for this design unit was generated from the following file:

• protocols/coaxpress/core/rtl/CoaXPressRxLaneMux.vhd