ClinkUartTb.test Architecture Reference

Architecture >> ClinkUartTb::test

Processes
comb	( r , rst , rxMaster , txSlave )
seq	( clk )
PROCESS_245	( failed , passed )

Constants
AXIS_CONFIG_C	AxiStreamConfigType := ( TSTRB_EN_C = > false , TDATA_BYTES_C = > 4 , TDEST_BITS_C = > 0 , TID_BITS_C = > 0 , TKEEP_MODE_C = > TKEEP_COMP_C , TUSER_BITS_C = > 2 , TUSER_MODE_C = > TUSER_FIRST_LAST_C )
CLK_PERIOD_C	time := 5 . 000 ns
TPD_G	time := 1 ns
REG_INIT_C	RegType := ( passed = > ' 0 ' , failed = > ' 0 ' , rxSlave = > AXI_STREAM_SLAVE_INIT_C , txMaster = > AXI_STREAM_MASTER_INIT_C , state = > TX_S )

Types
StateType	( TX_S , RX_S , FAIL_S , PASS_S )

Signals
r	RegType := REG_INIT_C
rin	RegType
clk	sl
rst	sl
loopback	sl
txMaster	AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C
txSlave	AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C
rxMaster	AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C
rxSlave	AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C
passed	sl := ' 0 '
failed	sl := ' 0 '

Records
RegType

Instantiations
u_clkrst	ClkRst <Entity ClkRst>
u_uart	ClinkUart <Entity ClinkUart>

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The documentation for this design unit was generated from the following file:

• protocols/clink/tb/ClinkUartTb.vhd