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ClinkFramerTb.test Architecture Reference
Architecture >> ClinkFramerTb::test

Processes

PROCESS_236  ( sysClk )

Constants

AXIS_CONFIG_C  AxiStreamConfigType := ( TSTRB_EN_C = > false , TDATA_BYTES_C = > 16 , TDEST_BITS_C = > 0 , TID_BITS_C = > 0 , TKEEP_MODE_C = > TKEEP_COMP_C , TUSER_BITS_C = > 2 , TUSER_MODE_C = > TUSER_FIRST_LAST_C )
CLK_PERIOD_C  time := 5 . 000 ns
TPD_G  time := 1 ns

Signals

sysClk  sl
sysRst  sl
parData  Slv28Array ( 2 downto 0 )
parValid  slv ( 2 downto 0 )
parReady  sl
dataMaster  AxiStreamMasterType
dataSlave  AxiStreamSlaveType
testCount  slv ( 7 downto 0 )
sUartMaster  AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C
sUartSlave  AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C
mUartMaster  AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C
loopback  sl
chanConfig  ClChanConfigType := CL_CHAN_CONFIG_INIT_C
chanStatus  ClChanStatusType := CL_CHAN_STATUS_INIT_C
linkStatus  ClLinkStatusArray ( 2 downto 0 ) := ( others = > CL_LINK_STATUS_INIT_C )

Instantiations

u_clkrst  ClkRst <Entity ClkRst>
u_framing  ClinkFraming <Entity ClinkFraming>
u_uart  ClinkUart <Entity ClinkUart>

The documentation for this design unit was generated from the following file: