BoxcarIntegrator.rtl Architecture Reference

Architecture >> BoxcarIntegrator::rtl

Processes
comb	( ibData , ibDataE , ibValid , intCount , obAck , r , ramDoutE , rst )
seq	( clk , rst )
comb	( ibData , ibDataE , ibValid , intCount , obAck , r , ramDoutE , rst )
seq	( clk , rst )

Constants
ACCUM_WIDTH_C	positive := ( DATA_WIDTH_G+ ADDR_WIDTH_G )
REG_INIT_C	RegType := ( obFull = > ' 0 ' , intCount = > ( others = > ' 0 ' ) , rAddr = > ( others = > ' 0 ' ) , wAddr = > ( others = > ' 0 ' ) , ibValid = > ' 0 ' , ibData = > ( others = > ' 0 ' ) , obValid = > ' 0 ' , obPeriod = > ' 0 ' , obData = > ( others = > ' 0 ' ) , ibDataE = > ( others = > ' 0 ' ) , obFullD = > ' 0 ' , ibValidD = > ' 0 ' , obPeriodD = > ' 0 ' )

Signals
r	RegType := REG_INIT_C
rin	RegType
ramDout	slv ( DATA_WIDTH_G- 1 downto 0 )
ramDoutE	signed ( DATA_WIDTH_G downto 0 )
ibDataE	signed ( DATA_WIDTH_G downto 0 )
rAddr	slv ( ADDR_WIDTH_G- 1 downto 0 )
wAddr	slv ( ADDR_WIDTH_G- 1 downto 0 )

Records
RegType

Instantiations
u_ram	SimpleDualPortRam <Entity SimpleDualPortRam>
u_ram	SimpleDualPortRam <Entity SimpleDualPortRam>

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/BoxcarIntegrator.vhd
• dsp/generic/fixed/BoxcarIntegrator.vhd