BoxcarIntegratorTb.testbed Architecture Reference

Architecture >> BoxcarIntegratorTb::testbed

Processes
PROCESS_99	( clk )
PROCESS_100
PROCESS_101	( clk )
PROCESS_102	( failed , passed )
PROCESS_211	( clk )
PROCESS_212
PROCESS_213	( clk )
PROCESS_214	( failed , passed )

Constants
TPD_G	time := 2 . 5 ns
DOB_REG_C	boolean := true

Signals
clk	sl := ' 0 '
rst	sl := ' 0 '
intCount	slv ( 9 downto 0 )
obPeriod	sl
obValid	sl
obFull	sl
obData	slv ( 25 downto 0 )
validCnt	slv ( 15 downto 0 )
validEn	sl
dataIn	slv ( 15 downto 0 )
expData0	slv ( 25 downto 0 )
expData1	slv ( 25 downto 0 )
expData2	slv ( 25 downto 0 )
expError	sl
spacing	slv ( 15 downto 0 )
passed	sl := ' 0 '
failed	sl := ' 0 '

Instantiations
u_clkrst	ClkRst <Entity ClkRst>
u_boxcarintegrator	BoxcarIntegrator <Entity BoxcarIntegrator>
u_clkrst	ClkRst <Entity ClkRst>
u_boxcarintegrator	BoxcarIntegrator <Entity BoxcarIntegrator>

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/BoxcarIntegratorTb.vhd
• dsp/generic/tb/BoxcarIntegratorTb.vhd