AxisToJtag.AxisToJtagImpl Architecture Reference

Architecture >> AxisToJtag::AxisToJtagImpl

Functions
boolean	xidIsNew ( data: in in slv xid: in in XidType memValid: in in boolean )
boolean	checkLen ( data: in in slv )

Processes
P_MUX_TDI	( mAxisReq , r , s )
P_TKEEP	( s )
P_COMB	( mAxisReq , memOut , r , s )
P_RAM	( axisClk )
P_SEQ	( axisClk )

Procedures
	setQueryData( wordLength: in natural range 4 to 16 memDepth: in natural range 0 to 65535 data: inout slv )
	sendHeaderNow( v: inout RegType )

Constants
WORD_SIZE_C	positive := 8 * AXIS_WIDTH_G
ADDR_ZERO_C	AddrType := ( others = > ' 0 ' )
LOCL_OSTRM_PORT	natural := 0
JTAG_OSTRM_PORT	natural := 1
TCK_FREQ_REF_C	real := 2 . 0E + 8
TCK_FREQ_C	real := ite ( AXIS_FREQ_G = 0 . 0 , TCK_FREQ_REF_C , AXIS_FREQ_G/ ( 2 . 0 * real ( CLK_DIV2_G ) ) )
TCK_LOG_RAT_C	real := ieee.math_real.log10 ( TCK_FREQ_REF_C/ TCK_FREQ_C )
TCK_BITS_C	natural range 0 to 255 := natural ( ieee.math_real.round ( TCK_LOG_RAT_C* 256 . 0 / 4 . 0 ) )
REG_INIT_C	RegType := ( state = > IDLE_S , nstate = > IDLE_S , replyData = > AXI_STREAM_MASTER_INIT_C , tLastSeen = > ' 0 ' , ackInput = > ' 0 ' , passTdo = > ' 0 ' , passTdi = > ' 0 ' , ridx = > ADDR_ZERO_C , widx = > ADDR_ZERO_C , memValid = > false , xid = > ( others = > ' 0 ' ) )

Types
MemType	( 0 to MEM_DEPTH_G- 1 ) slv ( WORD_SIZE_C- 1 downto 0 )
StateType	( IDLE_S , SEND_REP_S , WAIT_STARTED_S , WAIT_HDR_READY_S , WAIT_STOPPED_S , REPLAY_S )

Subtypes
AddrType	unsigned ( bitSize ( MEM_DEPTH_G ) downto 0 )

Signals
r	RegType := REG_INIT_C
rin	RegType
s	CombSigType
bufMem	MemType
memOut	slv ( WORD_SIZE_C- 1 downto 0 )

Attributes
ram_style	string
ram_style	signal is MEM_STYLE_G

Records
RegType
CombSigType

Instantiations
u_mux	AxiStreamSelector <Entity AxiStreamSelector>
u_jtag	AxisToJtagCore <Entity AxisToJtagCore>

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The documentation for this design unit was generated from the following file:

• xilinx/xvc-udp/jtag/rtl/AxisToJtag.vhd