AxisToJtagCore Entity Reference

Inheritance diagram for AxisToJtagCore:

Collaboration diagram for AxisToJtagCore:

Entities
AxisToJtagCore.AxisToJtagCoreImpl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
numeric_std
StdRtlPkg	Package <StdRtlPkg>
AxiStreamPkg	Package <AxiStreamPkg>

Generics
TPD_G	time := 1 ns
AXIS_WIDTH_G	positive := 4
LEN_POS0_G	natural := 0
LEN_POSN_G	natural := 17
CLK_DIV2_G	positive := 8
TLAST_IGNORE_G	boolean := false

Ports
axisClk	in	sl
axisRst	in	sl
mAxisTmsTdi	in	AxiStreamMasterType
sAxisTmsTdi	out	AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C
mAxisTdo	out	AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C
sAxisTdo	in	AxiStreamSlaveType
running	out	sl
tck	out	sl
tdi	out	sl
tms	out	sl
tdo	in	sl

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The documentation for this design unit was generated from the following file:

• xilinx/xvc-udp/jtag/rtl/AxisToJtagCore.vhd