AxisToJtagCore.AxisToJtagCoreImpl Architecture Reference

Architecture >> AxisToJtagCore::AxisToJtagCoreImpl

Processes
P_COMB	( mAxisTmsTdi , r , sAxisTdo , tdiReady , tdoData , tdoReady , tdoValid , tdoValidLoc )
P_SEQ	( axisClk )

Constants
AXIS_BW_C	positive := 8 * AXIS_WIDTH_G
REG_INIT_C	RegType := ( state = > IDLE_S , tdi = > ( others = > ' 0 ' ) , tms = > ( others = > ' 0 ' ) , tdo = > ( others = > ' 0 ' ) , nBits = > 0 , nBitsTot = > ( others = > ' 0 ' ) , tdiValid = > ' 0 ' , sReady = > ' 1 ' , tdoValid = > ' 0 ' , tdoPass = > ' 1 ' , last = > false , tLastSeen = > false , iCnt = > ( others = > ' 0 ' ) , oCnt = > ( others = > ' 0 ' ) , tLast = > ' 0 ' , running = > ' 0 ' )

Types
StateType	( IDLE_S , GET_TMS_S , GET_TDI_S , SHIFT_S , ALIGN_S , DISCARD_S )

Signals
tdoData	slv ( AXIS_BW_C- 1 downto 0 )
r	RegType := REG_INIT_C
rin	RegType
tdiReady	sl
tdoValidLoc	sl
tdoValid	sl
tdoReady	sl

Records
RegType

Instantiations
u_jtag	JtagSerDesCore <Entity JtagSerDesCore>

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The documentation for this design unit was generated from the following file:

• xilinx/xvc-udp/jtag/rtl/AxisToJtagCore.vhd