JtagSerDesCore Entity Reference

Inheritance diagram for JtagSerDesCore:

Entities
JtagSerDesCore.JtagSerDesCoreImpl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
StdRtlPkg	Package <StdRtlPkg>

Generics
TPD_G	time := 1 ns
WIDTH_G	positive := 32
CLK_DIV2_G	positive := 8

Ports
clk	in	sl
rst	in	sl
numBits	in	natural range 0 to WIDTH_G- 1
dataInTms	in	slv ( WIDTH_G- 1 downto 0 )
dataInTdi	in	slv ( WIDTH_G- 1 downto 0 )
dataInValid	in	sl
dataInReady	out	sl
dataOut	out	slv ( WIDTH_G- 1 downto 0 )
dataOutValid	out	sl
dataOutReady	in	sl
tck	out	sl
tdi	out	sl
tms	out	sl
tdo	in	sl

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The documentation for this design unit was generated from the following file:

• xilinx/xvc-udp/jtag/rtl/JtagSerDesCore.vhd